1. Field of the Invention
This invention relates to electronic devices, and more particularly to sense amplifiers.
2. Field of Related Art
Sense amplifiers are widely used to amplify output signals of memory circuits. FIG. 1 shows a diagram of a typical device using a sense amplifier 8. Circuit 16 may be a memory cell, a combination of memory cells whose outputs are ANDed (say, a PLD), or some other device which has a product term ("PT") output 12 and a product term ground ("PG38 )output 14. PT 12 can be high, for example 2.2 V, or low, for example 1.6 V. Sense amplifier 8 includes a p-channel pull-up transistor 34 and an n-channel pull-down transistor 36. Pull-up transistor 34 has a source 61 connected to a positive voltage supply VDD and a gate 51 connected to a voltage supply VREFP. Pull-down transistor 36 has a gate 31 connected to a constant voltage supply (not shown). Transistors 34 and 36 are always on. Circuit 16 can act as a switch to connect PT 12 to PTG 14 or to disconnect them from each other. When circuit 16 disconnects PT 12 from PTG 14, PT 12 is kept high by the voltage supply VDD through pull-up transistor 34. When circuit 16 connects PT 12 to PTG 14, PT 12 is driven low by the current through pull-down transistor 36.
PT 12 is amplified by buffer 18 whose output 120 can be high, for example 5 V, or low, for example 0 V.
FIG. 2 shows a prior art device with sense amplifier 8 in greater detail. Circuit 16 is an n-channel transistor which either connects PT 12 to PTG 14 or disconnects them from each other depending on the voltage on its gate 69. PT 12 is connected to buffer 18 through an n-channel pass transistor 66. Buffer 18 includes inverters 5 and 6. Inverter 6 includes a p-channel transistor 58 whose source 11 is connected to a constant positive voltage supply (not shown), and an n-channel transistor 60 whose source is connected to the ground. Buffer 18 also includes an n-channel feedback transistor 62 and a p-channel feedback transistor 64. Drain 21 of feedback transistor 62 is connected to a positive voltage supply (not shown). Feedback transistors 62 and 64 stabilize the voltage at node 19. When the voltage on node 19 goes too high, node 17 connected to the gates of feedback transistors 62 and 64 goes too low. As a result, the current through transistor 62 goes down, and the current through transistor 64 goes up. This pulls the voltage at node 19 down until the voltage at node 19 reaches its normal value. When the voltage at node 19 becomes too low, the voltage at node 17 is pulled up high. As a result, the current through feedback transistor 64 goes down, and the current through feedback transistor 62 goes up. This pulls the voltage at node 19 up to its normal value.
FIG. 3 shows another circuit with a sense amplifier. Buffer 18 includes inverters 3 and 4. Inverter 3 includes a p-channel transistor 44 and an n-channel transistor 46. Inverter 4 includes a p-channel transistor 40 and an n-channel transistor 42. Buffer 18 further includes an n-channel feedback transistor 50 and an n-channel feedback transistor 48.
FIG. 4 shows another device using a sense amplifier. Here circuit 16 includes an EEPROM cell 10 and a transistor 24 whose gate is connected to a row line. PT 12 is connected to the gate of pull-down transistor 36. PTG 14 is connected through pull-down transistor 36 to the drain of another pull-down transistor 28. The source of transistor 28 is connected to the ground. The gate of transistor 28 is connected to a positive voltage supply (not shown). The gate of clamp transistor 26 is connected to PT 12 through pass transistor 66. Buffer 18 comprises inverters 20 and 22. Inverter 20 comprises a p-channel transistor 39 and an n-channel transistor 38. VREFP is generated by voltage divider 57 of which VDD is an input. As a result, VREFP tracks VDD; when VDD increases, so does VREFP.
FIG. 5 diagrams PT 12 and output 120. When PT 12 rises from the low level VIL of 1.6 V to the high level VIH of 2.2 V as shown in FIG. 5(a), output 120 rises from 0 V to 5.0 V. The steeper is the rising edge 70 of PT 12, the steeper is the rising edge 71 of output 120 and so the faster is the sense amplifier on low-to-high transitions. When PT 12 falls from high to low as shown in FIG. 5(b), output 120 falls also. The steeper is the falling edge 75 of PT 12, the steeper is the falling edge 76 of output 120 and so the faster is the sense amplifier on high-to-low transitions.
It is desirable to provide a faster sense amplifier, and so it is desirable to provide steeper edges 71 and 76. It is also desirable to reduce the power consumption of a sense amplifier.
When the voltage on PT 12 changes between its low value VIL, say, 1.6 V, and its high value VIH, say, 2.2 V, buffer 18 switches output 120 at some intermediate input threshold voltage VTH, say 1.9 V. The relationship between VIL, VIH and VTH is shown in FIG. 6. The difference ("noise margin") 23 between VIH and VTH determines the tolerance of sense amplifier 8 to noise when PT 12 is high. The difference ("noise margin") 33 between VTH and VIL determines the tolerance of sense amplifier 8 to noise when PT 12 is low. As shown in FIG. 6(a), voltage VTH is usually near the middle between VIL and VIH, so that the noise margins 23 and 33 are about equal. At low operating temperatures, say at 0.degree. C., the threshold voltage VTH decreases. See FIG. 6(b). Another factor that can decrease voltage VTH is an increase, even by 5%, in voltage VDD on the source of pull-up transistor 34. When voltage VTH decreases, noise margin 33 between VTH and VIL also decreases. As a result, the sense amplifier becomes less reliable because it becomes more sensitive to noise on PT 12 when PT 12 is low. To keep noise margin 33 wide, sense amplifiers are made so that the total difference ("window") 43 between VIH and VIL is large. This can be achieved, for example, by enlarging the transistors in the sense amplifier. Yet increasing window 43 between voltages VIH and VIL makes the device using the sense amplifier slower, because it takes longer to switch between voltages VIH and VIL which are far apart. It is desirable to provide a sense amplifier fast and reliable both in normal conditions and at low temperatures and high VDD voltage supplies. It is desirable in general to decrease the noise sensitivity in a sense amplifier.
Some sense amplifiers use feedback circuitry to stabilize voltages. Transistors 62 and 64 in FIG. 2 form such a circuit. Yet many feedback circuits have only a limited application because they are intolerant to process variations. Feedback circuits usually include both p-channel and n-channel transistors manufactured during different process steps. The ratio between the p- and n-channels is crucial for the correct operation of the feedback circuit. If, due to process variations, p-channels are too large, many feedback circuits are unreliable. It is desirable to provide a sense amplifier more tolerant to process variations.
Circuit 16 may be a combination of memory cells whose outputs are ANDed together. Circuit 16 of FIG. 7 has EEPROM memory cells like cell 53. Each cell is connected to PT 12 through a transistor like transistor 63. If all memory cells like cell 53 are programmed to conduct, and row line 45 is high, PT 12 is driven very low, possibly below 1.6 V. As a result, the transition of PT 12 from low to high (when row line 45 goes from high to low) is especially slow. A similar problem occurs on high-to-low transitions if only one of the memory cells is programmed to conduct. In that case, when row line 45 changes from low to high, PT 12 is driven from high to low by only one conducting memory cell. This transition is quite slow. It is desirable to provide a sense amplifier which provides fast transitions of output 120 when circuit 16 is a combination of memory cells of FIG. 7.